Tim Waugh (firstname.lastname@example.org)
Tue, 16 Mar 1999 11:49:05 -0000
> >Tell that to NatSemi et al. I don't know why there
> >is no hardware facility
> >for reading an ECP channel.
> Read: Its an address if PeriphAck is Low when the hardware
> read is done, or data if PeriphAck is High.
> Write: Its an address if HostAck is Low when the hardware
> write is done, or data if HostAck is High.
Okay, I've just looked up the datasheet for the PC87332 on www.natsemi.com.
Take a look at page 76 -- there is a table of the ECP registers. DFIFO (ECP
Data FIFO) is R/W, while AFIFO (ECP Address FIFO) is W.
In the text, it also says that DTR, STR and CTR are not accessible when ECP
Page 79 also has this:
"When the ECP is in the backward direction and the FIFO is not full (bit 1
of ECR is 0), the ECP issues a read cycle from the peripheral device and
monitors the BUSY signal. If BUSY is high the byte is a data byte and it is
pushed into the FIFO. If BUSY is low the byte is a command byte. The ECP
checks bit 7 of the command byte, if it is high the byte is ignored, if it
is low the byte is tagged as an RLC byte (not pushed into the FIFO but used
as a Run Length Count to expand the next byte read). Following an RLC read,
the ECP issues a read cicle from the peripheral to read the data byte to be
expanded. This byte is considered a data byte, regardless of its BUSY state
(even if it is low). This byte is pushed into the FIFO (RLC+1) times (i.e.,
RLC=0: push the byte once, RLC=127: push the byte 128 times)."
It seems pretty clear that NatSemi chips will make a mess of any driver for
a device that sends ECP addresses to the host, so mixing hardware and
software is definitely out, because it won't work, at least with that chip.
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This archive was generated by hypermail 2.0b3 on Sun 28 Mar 1999 - 17:00:54 EST