I've found an interesting problem with my current parport device. I've
got a device that works reliably until I start doing IDE transfers. In
particular, IDE write operations seem to be a problem.
The symptom is that the peripheral appears to not see the host strobe
for a written byte. So the PC goes into timeout on the write (which
then leads to a problem because the device does not comply with IEEE
1284 on host aborts, bleah). I've only caught the after failure view on
the logic analyzer. It showed that the PC is asserting the strobe, and
that the peripheral is not acknowledging it. I have not yet figured out
how to trigger the analyzer on something that will show the actual
failure, so I do not know whether strobe timings, widths, etc. are to
spec or not.
Does anyone have any prior experience with IDE activity interfering with
parallel IO?
My present test environment is to do continuous peripheral
command/response cycles. It has a "read register" that is reasonably
fast and I can verify that the register contents are correct. On a
really quiescent system I let it run about 8 million cycles (each
complete command/response takes about 250 usec). Then I did some fairly
routine copy files around and triggered the problem within 15 seconds.
That's about 50K read/write cycles.
Next step is to see whether a modified retry recovery deals with this,
but it would help if someone could suggest how IDE is causing this. I
am assuming that an IDE interrupt hits at the wrong time and really
messes up the timing with a block data move. This should not cause a
problem, but somehow it seems to. This is using software implemented
ECP logic, so the dual handshake should deal with delays.
It is not something simple like lots of interrupts. During that 8
million cycle test I did an ethernet ping flood of the machine (about
3000 pings/sec 64bytes per ping, 98% echoed OK) for several minutes. No
problem.
R Horn
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