Perhaps but aren't PCI interrupts level sensitive? OTOH these PCI
parrallel boards I think are ISA ASICs with PCI glue. So the ASIC
generates an IRQ signal and sense it's an ECP interrupt resets the
interrupt condition turning off the interrupt signal? But why wouldn't
this be an issue with the built in mother board parrallel ports? BTW, I
do think the 8259 is implemented as part of the SiS530 chipset.
Any clue as to what the timings on this would be? The system was in
single user mode so no extraneous activity -- an idle system.
Gunther Mayer wrote:
> Tom Perkins wrote:
>
> ....
>
>>I forced the interrupt for the slot from IRQ5 to IRQ12 with equivalent
>>results. When forced to IRQ7 everything did report solely on IRQ7.
>>
>>I'm somewhat at a loss to explain this behavior. My first guess would be
>>a board flaw. But I fail to understand how the board could be generating
>>an interrupt on IRQ7. If it was a INTA/INTB issue I'd expect an IRQ
>>other than IRQ7. The boards INTB should show up as INTA on an adjacent
>>board right? So with the spurious interrupts showing up only on IRQ7 I
>>have to wonder if it's not a motherboard chipset quirk of some type?
>>
>
>>From "Harris Semiconductor 82C59A Interrupt Controller":
> If no interrupt request is present at step 4 of either sequence
> (i.e., the request was too short in duration), the 82C59A will
> issue an interrupt level 7.
>
> 1. The irq controller sees an interrupt.
> 2. The irq controller signals "there is _some_ interrupt" to the cpu.
> 3. The CPU acks via INTA
> 4. The irq controller looks if the irq is still there
> (and signals IRQ7 if the line is no longer active).
>
>
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This archive was generated by hypermail 2b29 : Fri Nov 30 2001 - 13:25:02 EST