Hi Tim and All,
Per Tim's suggestion I've been working on code to provide PPF and ECP
PIO support with no reliance on interrupts. I've been working against
the parport_pc modules in 2.4.14. I've reached a point where I need
some questions answered.
In the function parport_pc_compat_write_block_pio
1.) The setting of the phase to FWD_DATA and FWD_DATA_IDLE would seem
incorrect?
2.) Changing the mode to ECR_TST looks illegal -- Violates the rule that
ECR_PS2 must be visited first? This code is the same for the
ecp_write_block code. In the MS version of 1284 spec I thought a
control single STROBE was used to stop transfer? Is this correct and
what should be used for compat_write_block?
CODE FRAGMENTS:
/* Parallel Port FIFO mode (ECP chipsets) */
size_t parport_pc_compat_write_block_pio (struct parport *port,
.
.
.
port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; <----???
.
.
.
printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
/* Prevent further data transfer. */
frob_econtrol (port, 0xe0, ECR_TST << 5); <--------????
.
.
.
port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; <----??
.
.
.
return written;
}
Regards,
Tom
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