On 05-Sep-00 David Dillow wrote:
>> so what you are saying is that the ECP for example does not follow the IEEE
>> 1284 standard? What I have to do is transfer data from a FPGA (I have to
>> program) to a parallel port. I have developed the code to logically link my
>> PC
>> to the FPGA... hope the protocolo listed in IEEE 1284 is the right one (with
>> negotiation/setup/forward-reverseMode).
>>
>> I will check the references you gave me. Thank you very much David.
>
> Well, actually, I think it was adopted by 1284 -- you'll have to forgive
> me, it's been a while since I've played in this space... there is code
> in drivers/parport/ieee1284.c to handle ECP mode, so I guess it's part
> of the standard.... :/
>
> In any event, here's the specs I promised...
> Enjoy!
> D
Hi David,
I read them. Thank you for your help.
There are some things I do not understand:
1) in ECP mode the negotiation is done
by the hardware chip or do I have to drive the signals to pilot the negotiation
in software?
2) the most interesting question regards 'how to I read (Peripheral to Host -
ECP reverse mode)' in ECP mode? Is it enought to inport one byte from the ECP
FIFO? Again in this case who is performing the negotiation for Forward to
Reverse mode?
Thank you and Best Regards,
Andrea Aizza.
----------------------------------------
Andrea AIZZA
----------------------------------------
Swiss Federal Institute of Technology
Department of Electrical Engineering
Integrated Systems Center (LSI)
EPFL-DE-LSI Office: ELB-137
Ecublens, CH-1015 Lausanne (CH)
tel. +41 21 693 69 73
fax. +41 21 693 46 63
email Andrea.Aizza@epfl.ch
http://lsiwww.epfl.ch/
----------------------------------------
-- To unsubscribe, send mail to: linux-parport-request@torque.net --
-- with the single word "unsubscribe" in the body of the message. --
This archive was generated by hypermail 2b29 : Mon Sep 11 2000 - 05:27:07 EDT