I'm having a problem issuing an EPP DATA read on a VIA 686B system. The
Linux kernel version is 2.4.20, but I don't think it matters much, since
most of the stuff I'm doing is using inb/outb.
I can issue the EPP ADDR read and write, and I can issue an EPP DATA write.
What's strange is that rhe EPP DATA read consistently fails and the EPP
timeout bit is set. The bit clears fine.
The host is connected to an FPGA device. The initial development was done
under Win32 (NT, to be exact) using a different host, and the FPGA works
fine in that configuration, so I have to assume the FPGA works as intended.
I have tried as variety of things, like constantly programming the EPP mode
on the control register:
before issuing the EPPDATA read. No change. I have also tried doing the
ECPEPP type operations that program the ECR, the control reg, and toggle the
data direction bit (after changing the port mode in the BIOS). That has not
worked for me either.
I have tried inserting delays before the read ranging from 20 microseconds
to 1 millisecond, and the read still fails.
I would like to know your overall opinion of this problem as stated. At this
point, I'm very suspect of the host hardware. I'm prepping up a couple of
other hosts: one with the same type of hardware, and one based on the Intel
Am I missing something? Your feedback is always appreciated.
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This archive was generated by hypermail 2b29 : Mon Apr 21 2003 - 16:55:01 EDT