From: Peter Asemann (sipeasem@immd3.informatik.uni-erlangen.de)
Date: Tue Jun 17 2003 - 10:49:37 EDT

  • Next message: Tim Waugh: "Re: [PARPORT] ECR/ECP FIFO questions"

    An ECP host controller has some FIFOs - for data transfers, address transfers
    and the test FIFO.
    I guess that in hardware there are three FIFOs - The test FIFO, a combined
    address/data mode output FIFO and a combined address/data mode input FIFO.

    To keep the data/address to be written in the right order (important for RLE)
    I guess that the data/address output fifo is 9 bit wide so there are 8 bits
    for data and one bit to indicate if it's an address mode or a data mode byte.

    There are ways to read the address/data FIFO, too - so there probably is a
    FIFO in the ECP host controller hardware which takes bytes from the
    peripheral and also saves them in 9 bit to keep the bytes in order.
    This FIFO can probably be read under two different addresses, the address of
    the ECP address fifo (base address + 0) and the ECP data fifo (base-hi + 0).

    If find that's interesting... if there are some address bytes and some data
    bytes in the (probably shared) FIFO, will you be able to read them out in the
    wrong order?
    Is it possible to read anything from the ECP address FIFO anyway? There could
    be activated RLE decompression, so there'd never be anything to read in the
    ECP address FIFO. There seems not to be a way to deactivate RLE decompression
    if your port has that feature.
    Are there ECPs that don't have RLE decompression?
    Even Jan Axelson seems not to be sure where the ECP host controller hardware
    puts the bytes received from the peripheral exactly on page 291 of his book
    "parallel port complete" when he simply speaks of "the FIFO".

    In the ECR are 2 bit reserved for monitoring the FIFO status - bit 0
    (FIFOEmpty) shows if the (input) FIFO is empty or if there is at least one
    byte of data to be read.
    Bit 1 shows if the (output) FIFO is full or if there is at least one byte
    free to write.
    So another question is - is there any way to know if there is a data or an
    address byte waiting in the FIFO to be read?
    Only knowing there is a byte waiting to be read in the FIFO I cannot know if
    I am supposed to read the data or the address FIFO?

    Or is it so that in fact you can never have an ECP without RLE decompression,
    the ECP address FIFO cannot ever be read, and so the ECR fifo indicator bit
    for incoming bytes always refers to the ECP data fifo?

    Thanks in advance and for reading

    Peter Asemann

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