Hi,
There seens to be a bug(?) in the (Experimental) super-io support for Via C686A
chipset in parport_pc.c. ("maintained by Jeff Garzik").
This code is in 2.4.x >=14 and 2.6.0-test kernels
See code snippet below. "have_ecp" is read from F0 "Parallel Port Control"
register (I'm looking at the Via data sheet) and defaults to the value 0x00
The sio_via_686_probe() seems to think that if it doesn't find a "1" at bit 5,
ecp is not available. This is not true in my case (Ahlon with a Via
motherboard). In the code below, the attempt to use ecp+dma is abandoned
if "have_ecp" = 0x00. In fact, just commenting out this test allows my
ECP/DMA port to get activated by sio_via_686_probe() and works just fine.
Does this code work for anyone with Via C686?
How is the F0 register supposed to have got a non-0x00 value?
Can Jeff or anyone else advise me about this?
Thanks
Duncan Haldane
/* Via support maintained by Jeff Garzik <jgarzik@pobox.com> */
static int __devinit sio_via_686a_probe (struct pci_dev *pdev, int autoirq,
int autodma)
{
u8 tmp;
int dma, irq;
unsigned port1, port2, have_eppecp;
/*
* unlock super i/o configuration, set 0x85_1
*/
pci_read_config_byte (pdev, 0x85, &tmp);
tmp |= (1 << 1);
pci_write_config_byte (pdev, 0x85, tmp);
/*
* Super I/O configuration, index port == 3f0h, data port == 3f1h
*/
/* 0xE2_1-0: Parallel Port Mode / Enable */
outb (0xE2, 0x3F0);
tmp = inb (0x3F1);
if ((tmp & 0x03) == 0x03) {
printk (KERN_INFO "parport_pc: Via 686A parallel port disabled
in BIOS\n");
return 0;
}
/* 0xE6: Parallel Port I/O Base Address, bits 9-2 */
outb (0xE6, 0x3F0);
port1 = inb (0x3F1) << 2;
switch (port1) {
case 0x3bc: port2 = 0x7bc; break;
case 0x378: port2 = 0x778; break;
case 0x278: port2 = 0x678; break;
default:
printk (KERN_INFO "parport_pc: Weird Via 686A parport base
0x%X, ignoring\n",
port1);
return 0;
}
/* 0xF0_5: EPP+ECP enable */
outb (0xF0, 0x3F0);
have_eppecp = (inb (0x3F1) & (1 << 5));
<snip>
/* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
if (!have_eppecp)
dma = PARPORT_DMA_NONE;
----------------------------------
E-Mail: Duncan Haldane <f.duncan.m.haldane@worldnet.att.net>
Date: 03-Oct-2003
Time: 03:22:27
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