Re: [PARPORT] Question about 2.4.0-test1 FIFO reads

Date: Wed Jul 05 2000 - 11:28:06 EDT

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    Further info on FIFO. The Super-IO chipset specification is clearer. It
    implies that the hardware does do what we need. The exact words are:

        When the ECP is in the backward direction, and the FIFO is
        not full (bit 1 of ECR is 0), the ECP issues a read cycle to
        the peripheral device and monitors the BUSY signal. If
        BUSY is high the byte is a data byte and it is pushed into the
        FIFO. If BUSY is low the byte is a command byte.

    This implies that the chip will hold off ECP cycles while FIFO is full.
    The overrun consideration is from the peripheral. The peripheral might
    not be able to wait. For example, the integrated FDC controller cannot
    wait. It obtains data in bit serial from the floppy disk logic, forms
    bytes, and shoves them into the FIFO. If the FIFO cannot keep up, it
    discards bytes and turns on a data overrun flag.

    If this is the case for all the other chipsets (which seems likely given
    that the old Super-IO is emulated by some of them) the FIFO mode logic
    can be made simpler. The Super-IO is also clear that you should not
    transition the direction when there are bytes in the FIFO. It too will
    fail. So the early turn-around to eliminate the race condition is not a

    R Horn

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