Re: Super IO-Chips, was Re: [PARPORT] Probing for Super-IO Chips ...

From: Gunther Mayer (Gunther.Mayer@t-online.de)
Date: Wed Mar 21 2001 - 14:13:29 EST

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    Uwe Bonnes wrote:
    >
    > >>>>> "Gunther" == Gunther Mayer <Gunther.Mayer@t-online.de> writes:
    >
    > Gunther> Uwe Bonnes wrote:
    > >> Writing on some items would be allowed in some situations, like "echo
    > >> "ppaddr 278" >/proc/superio/0 would change the parallel port address,
    > >> if the old adress isn't actual used.
    > >>
    > >> Exporting the Super IO Chip registers and decoding these in a user
    > >> programm would be another possibility. However I feel bad about
    > >> letting the user program write random registers...
    > >>
    >
    > I had posted something like this for some SMC chip around 1996 named
    > smcio.c, but got nearly no few feedback. As I saw these superio things in
    > parport_pc, my interest got up again.
    >
    > Gunther> Don't overdesign the kernel superio interface, my original
    > Gunther> intent was to detect IRQ and DMA for parport. (This has been
    > Gunther> nearly obsoleted by my lastest PNPBIOS and ACPI patches.)
    >
    > Are these patches in 2.4.2.pre3? If not, I can I have a look at them.
    >

    Here are my latest patches (sent to this list some time ago):
    1) http://home.t-online.de/home/gunther.mayer/gmdiff-lx242-parport+acpi+pnpbios-0.02

     I would like to get PNPBIOS+ACPI to the current kernel. Alan Cox is
     be interested, if the GDT-Hack in PNPBIOS is removed (allocate own GDT
     for PNPBIOS and don't fiddle with APMBIOS's GDTs). HELP appreciated on this !

    2) http://home.t-online.de/home/gunther.mayer/Superio6-240t11p3-parport.patch

     This was not tested very much (I received 2 patches, 4 reports total). With
     proper PNPBIOS support in the kernel, this could easily live in user space
     (although for parport it would print out some valuable information e.g.
      totem pole vs. open drain, which would explain why you get different behaviour
      concerning legacy transfer modes on some chips).

    -
    Regards, Gunther

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