Carlos Henrique Bauer (chbauer@acm.org)
Thu, 29 Apr 1999 21:56:02 -0300
The SPP detection code that appears in the parallel port book I own resets the
control port bit 5 before doing the write/read test. If the port is a
PS/2 port and the control port bit 5 is set during test, the outputs will be
tri-stated and the value that is read back won't match what was written.
On Thu, 29 Apr 1999, you wrote:
>The SPP detection code in my tree was modified not long ago in order to
>detect Thomas Ruth's port, although it now seems that 2.2.4 can detect it
>fine(!). This new failure to detect a port still happens with the SPP
>modifications.
>
>Basically, the new SPP code writes 0x0c to ctr, writes to data and tries to
>read it back. If it sees something different, it assumes that the port
>doesn't latch data, and moves on to the control register. If it can read
>back enough bits from there, we really have a port there. I think it needs
>the low seven bits (on my machine, the top bit cannot be set). But it may
>be that this port doesn't allow us to read the control register.
>
>If the data register and control register tests both fail, but the user has
>specified the address, we assume they know what they're talking about.
>Otherwise, no port.
Best regards,
--Carlos Henrique Bauer
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This archive was generated by hypermail 2.0b3 on Thu 29 Apr 1999 - 23:09:27 EDT