Tim Waugh (tim@cyberelk.demon.co.uk)
Fri, 30 Apr 1999 09:32:37 +0100 (GMT)
On Thu, 29 Apr 1999, Carlos Henrique Bauer wrote:
> The SPP detection code that appears in the parallel port book I own
> resets the control port bit 5 before doing the write/read test. If the
> port is a PS/2 port and the control port bit 5 is set during test, the
> outputs will be tri-stated and the value that is read back won't match
> what was written.
Yes. We should be okay there, because we write 0xc to CTR first, so bit 5
is 0.
Tim.
*/
-- To unsubscribe, send mail to: linux-parport-request@torque.net --
-- with the single word "unsubscribe" in the body of the message. --
This archive was generated by hypermail 2.0b3 on Fri 30 Apr 1999 - 07:35:02 EDT